The present invention is directed generally to frequency synthesizers.
Frequency synthesizers are widely used in modern radio communication systems. Such devices typically make use of a single quartz-controlled (i.e., crystal) reference oscillator combined with a phase-locked loop (PLL) to provide a multitude of output frequencies traceable to the highly stable reference from the oscillator.
FIG. 1 is a block diagram of a conventional digital PLL frequency synthesizer. A high frequency, tunable voltage controlled oscillator (VCO) 10 generates a signal (the “output signal”) that is fed to the output port of the device via a buffer amplifier 12. A sample of the output signal is fed via a high-speed prescaler 14 (such as a fixed modulus frequency divider) and a programmable (divide by N) divider 16 to a digital phase/frequency detector 18, which is typically comprised of a pair of D-type flip-flops. The phase/frequency detector 18 also receives a reference input signal from a reference divider 20.
Error signals in the form of pulse width modulated pulse trains are produced at the output port of the phase/frequency detector 18, which are fed to an active filter 22. The active filter 22 integrates the error signals to produce a voltage control signal used to control the VCO 10. When the PLL is locked, it acts as a servo system to maintain equal frequency signals at both inputs of the phase/frequency detector 18. Therefore, the output signal frequency signal will change if the division ratio of the programmable divider 16 (which is received by the programmable divider as a command signal) is changed.
The operation of this type of Integer-N PLL frequency synthesizer may be described mathematically. In particular,
                              F          loop                =                              F            out                    PxN                                    (        1        )            where Floop is the frequency of the output signal from the programmable divider 16, Fout is the frequency of the output signal, P is the division ratio of the prescaler 14, and N is the division ratio of the programmable divider 16. The PLL acts to maintain
                              F          loop                =                              F            ref                    R                                    (        2        )            where Fref is the frequency of the reference signal output from the reference divider 20 and R is the division ratio of the reference divider 20. Therefore,
                                                        F              ref                        R                    =                                    F              out                        PxN                          ⁢                                  ⁢        and                            (        3        )                                          F          out                =                                            F              ref                        ⁢            xPxN                    R                                    (        4        )            Differentiating equation (4) with respect to N yields:
                                          ⅆ                          F              out                                            ⅆ            N                          =                  Px          ⁢                                    F              ref                        R                                              (        5        )            This is the step size of the output signal or, in other words, the change in frequency in the output signal caused be changing the programmable division ratio N by one increment. Using the example frequencies and division ratios shown in FIG. 1, the phase comparison frequency may be calculated to be
      F    loop    =                    1750        ⁢                                  ⁢        MHz                    4        ×        8750              =          50      ⁢                          ⁢              kHz        .            
The PLL of FIG. 1 will exhibit an effective loop bandwidth determined by the time constant of the loop filter 22. Typically the loop bandwidth used in PLLs of this type is between ten and one hundred kilohertz.
The natural phase noise of the VCO 10 is suppressed at carrier-offset values less than the loop bandwidth. Phase noise performance in this region is normally limited by the so-called “phase comparator noise floor” (PCNF) of the phase/frequency detector 18. The PCNF represents the smallest difference in phase that the phase/frequency detector 18 can resolve and is normally expressed as a power level in a 1 Hz bandwidth relative to a reference carrier. The absolute PCNF of the best digital phase/frequency detectors available at this time is on the order of −213 dBc/Hz. The phase noise at the output of the PLL of FIG. 1 may be predicted mathematically to be:
      PCNF    output    =            PCNF      ⁡              (        abs        )              +          10      ⁢              log        10            ⁢              F        loop              +          20      ⁢                          ⁢                        log          10                ⁡                  (                                    F              out                                      F              comp                                )                    where PCNF(abs) is the absolute PCNF. For the PLL of FIG. 1, therefore,
            PCNF      output        =                  -        213            +              10        ⁢                              log            10                    ⁡                      (                          50              ×                              10                3                                      )                              +              20        ⁢                              log            10                    ⁡                      (                                          1750                ×                                  10                  6                                                            50                ×                                  10                  3                                                      )                                                  ⁢                  PCNF        output            ≈                        -          75                ⁢                                  ⁢        dBc        ⁢                  /                ⁢        Hz            for an output signal center frequency of 1750 MHz.
From the above, it can be seen that the PCNF is strongly dependent on the output frequency and the step size.
With this in mind, high capacity microwave radio systems often make use of “high density modulation” schemes, such as 128 QAM (128 state Quadrature Amplitude Modulation), which require the use of low noise oscillators in both the radio transmitter and receiver. Such radio systems also typically require digital tuning of both the transmit and receive frequencies. This combination of requirements has been satisfied with the use of frequency synthesizers based on either YIG (Yttrium Iron Gamate) tuned oscillators or so-called “composite sources,” formed by mixing signals from two or more oscillators. YIG synthesizers tend to be highly microphonic and produce phase hits (i.e., small but very rapid changes in the output signal frequency) when subjected to changing ambient temperature. Composite sources on the other hand are complex and tend to be expensive to produce.
Accordingly, there exists a need for a frequency synthesizer operable at high frequencies (such as microwave frequencies) that is capable of being tuned in very small frequency steps while maintaining excellent phase noise performance.